// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  ts_sysctrl_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Version       :  1.0
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2
// ******************************************************************************

#ifndef __TS_SYSCTRL_REG_OFFSET_FIELD_H__
#define __TS_SYSCTRL_REG_OFFSET_FIELD_H__

#define TS_SYSCTRL_AXIECS0_DLOCK_MST_LEN    2
#define TS_SYSCTRL_AXIECS0_DLOCK_MST_OFFSET 20
#define TS_SYSCTRL_AXIECS0_DLOCK_SLV_LEN    3
#define TS_SYSCTRL_AXIECS0_DLOCK_SLV_OFFSET 16
#define TS_SYSCTRL_AXIECS0_DLOCK_ID_LEN     12
#define TS_SYSCTRL_AXIECS0_DLOCK_ID_OFFSET  4
#define TS_SYSCTRL_AXIECS0_DLOCK_WR_LEN     1
#define TS_SYSCTRL_AXIECS0_DLOCK_WR_OFFSET  1
#define TS_SYSCTRL_AXIECS0_DLOCK_IRQ_LEN    1
#define TS_SYSCTRL_AXIECS0_DLOCK_IRQ_OFFSET 0

#define TS_SYSCTRL_AXIECS0_PORT_BUSY_BUS_MASTER_LEN    3
#define TS_SYSCTRL_AXIECS0_PORT_BUSY_BUS_MASTER_OFFSET 8
#define TS_SYSCTRL_AXIECS0_PORT_BUSY_BUS_SLAVE_LEN     6
#define TS_SYSCTRL_AXIECS0_PORT_BUSY_BUS_SLAVE_OFFSET  0

#define TS_SYSCTRL_DBGACK_LEN           1
#define TS_SYSCTRL_DBGACK_OFFSET        7
#define TS_SYSCTRL_TS_CPU_NFIQ_LEN      1
#define TS_SYSCTRL_TS_CPU_NFIQ_OFFSET   6
#define TS_SYSCTRL_TS_CPU_NIRQ_LEN      1
#define TS_SYSCTRL_TS_CPU_NIRQ_OFFSET   5
#define TS_SYSCTRL_PMCCNTR_63BIT_LEN    1
#define TS_SYSCTRL_PMCCNTR_63BIT_OFFSET 4
#define TS_SYSCTRL_CUSTOM_WFE_LEN       1
#define TS_SYSCTRL_CUSTOM_WFE_OFFSET    1
#define TS_SYSCTRL_CUSTOM_WFI_LEN       1
#define TS_SYSCTRL_CUSTOM_WFI_OFFSET    0

#define TS_SYSCTRL_TS_IDLE_DIV_STAT_LEN    1
#define TS_SYSCTRL_TS_IDLE_DIV_STAT_OFFSET 0









#define TS_SYSCTRL_CNT_LOW32_LEN    32
#define TS_SYSCTRL_CNT_LOW32_OFFSET 0

#define TS_SYSCTRL_CNT_HIGH32_LEN    32
#define TS_SYSCTRL_CNT_HIGH32_OFFSET 0





#define TS_SYSCTRL_FCM_IDLE_LEN                         1
#define TS_SYSCTRL_FCM_IDLE_OFFSET                      14
#define TS_SYSCTRL_CORE_IDLE_LEN                        1
#define TS_SYSCTRL_CORE_IDLE_OFFSET                     13
#define TS_SYSCTRL_AWAKEUPM0_LEN                        1
#define TS_SYSCTRL_AWAKEUPM0_OFFSET                     12
#define TS_SYSCTRL_CLUSTERPWRSTAT_ACTIVE_PORTION_LEN    4
#define TS_SYSCTRL_CLUSTERPWRSTAT_ACTIVE_PORTION_OFFSET 8
#define TS_SYSCTRL_COREINSTRRET_LEN                     1
#define TS_SYSCTRL_COREINSTRRET_OFFSET                  7
#define TS_SYSCTRL_COREINSTRRUN_LEN                     1
#define TS_SYSCTRL_COREINSTRRUN_OFFSET                  6
#define TS_SYSCTRL_CLUSTERDBGPWRUPREQ_LEN               1
#define TS_SYSCTRL_CLUSTERDBGPWRUPREQ_OFFSET            5
#define TS_SYSCTRL_DBGPWRUPREQ_LEN                      1
#define TS_SYSCTRL_DBGPWRUPREQ_OFFSET                   4
#define TS_SYSCTRL_PMUSNAPSHOTACK_LEN                   1
#define TS_SYSCTRL_PMUSNAPSHOTACK_OFFSET                3
#define TS_SYSCTRL_CPU_DBGACK_LEN                       1
#define TS_SYSCTRL_CPU_DBGACK_OFFSET                    2
#define TS_SYSCTRL_CPU_CUSTOM_WFE_LEN                   1
#define TS_SYSCTRL_CPU_CUSTOM_WFE_OFFSET                1
#define TS_SYSCTRL_CPU_CUSTOM_WFI_LEN                   1
#define TS_SYSCTRL_CPU_CUSTOM_WFI_OFFSET                0

#define TS_SYSCTRL_PWR_QREQN_LEN           1
#define TS_SYSCTRL_PWR_QREQN_OFFSET        23
#define TS_SYSCTRL_PWR_QDENY_LEN           1
#define TS_SYSCTRL_PWR_QDENY_OFFSET        22
#define TS_SYSCTRL_PWR_QACTIVE_LEN         1
#define TS_SYSCTRL_PWR_QACTIVE_OFFSET      21
#define TS_SYSCTRL_PWR_QACCEPTN_LEN        1
#define TS_SYSCTRL_PWR_QACCEPTN_OFFSET     20
#define TS_SYSCTRL_PDBGTCLK_QREQN_LEN      1
#define TS_SYSCTRL_PDBGTCLK_QREQN_OFFSET   19
#define TS_SYSCTRL_PDBGTCLK_QDENY_LEN      1
#define TS_SYSCTRL_PDBGTCLK_QDENY_OFFSET   18
#define TS_SYSCTRL_PDBGCLK_QACTIVE_LEN     1
#define TS_SYSCTRL_PDBGCLK_QACTIVE_OFFSET  17
#define TS_SYSCTRL_PDBGCLK_QACCEPTN_LEN    1
#define TS_SYSCTRL_PDBGCLK_QACCEPTN_OFFSET 16
#define TS_SYSCTRL_SCLK_QREQN_LEN          1
#define TS_SYSCTRL_SCLK_QREQN_OFFSET       15
#define TS_SYSCTRL_SCLK_QDENY_LEN          1
#define TS_SYSCTRL_SCLK_QDENY_OFFSET       14
#define TS_SYSCTRL_SCLK_QACTIVE_LEN        1
#define TS_SYSCTRL_SCLK_QACTIVE_OFFSET     13
#define TS_SYSCTRL_SCLK_QACCEPTN_LEN       1
#define TS_SYSCTRL_SCLK_QACCEPTN_OFFSET    12
#define TS_SYSCTRL_PCLK_QREQN_LEN          1
#define TS_SYSCTRL_PCLK_QREQN_OFFSET       11
#define TS_SYSCTRL_PCLK_QDENY_LEN          1
#define TS_SYSCTRL_PCLK_QDENY_OFFSET       10
#define TS_SYSCTRL_PCLK_QACTIVE_LEN        1
#define TS_SYSCTRL_PCLK_QACTIVE_OFFSET     9
#define TS_SYSCTRL_PCLK_QACCEPTN_LEN       1
#define TS_SYSCTRL_PCLK_QACCEPTN_OFFSET    8
#define TS_SYSCTRL_GICCLK_QREQN_LEN        1
#define TS_SYSCTRL_GICCLK_QREQN_OFFSET     7
#define TS_SYSCTRL_GICCLK_QDENY_LEN        1
#define TS_SYSCTRL_GICCLK_QDENY_OFFSET     6
#define TS_SYSCTRL_GICCLK_QACTIVE_LEN      1
#define TS_SYSCTRL_GICCLK_QACTIVE_OFFSET   5
#define TS_SYSCTRL_GICCLK_QACCEPTN_LEN     1
#define TS_SYSCTRL_GICCLK_QACCEPTN_OFFSET  4
#define TS_SYSCTRL_ATCLK_QREQN_LEN         1
#define TS_SYSCTRL_ATCLK_QREQN_OFFSET      3
#define TS_SYSCTRL_ATCLK_QDENY_LEN         1
#define TS_SYSCTRL_ATCLK_QDENY_OFFSET      2
#define TS_SYSCTRL_ATCLK_QACTIVE_LEN       1
#define TS_SYSCTRL_ATCLK_QACTIVE_OFFSET    1
#define TS_SYSCTRL_ATCLK_QACCEPTN_LEN      1
#define TS_SYSCTRL_ATCLK_QACCEPTN_OFFSET   0

#define TS_SYSCTRL_CLUSTER_PACTIVE_LEN    20
#define TS_SYSCTRL_CLUSTER_PACTIVE_OFFSET 12
#define TS_SYSCTRL_CLUSTER_PSTATE_LEN     7
#define TS_SYSCTRL_CLUSTER_PSTATE_OFFSET  4
#define TS_SYSCTRL_CLUSTER_PREQ_LEN       1
#define TS_SYSCTRL_CLUSTER_PREQ_OFFSET    2
#define TS_SYSCTRL_CLUSTER_PDENY_LEN      1
#define TS_SYSCTRL_CLUSTER_PDENY_OFFSET   1
#define TS_SYSCTRL_CLUSTER_PACCEPT_LEN    1
#define TS_SYSCTRL_CLUSTER_PACCEPT_OFFSET 0

#define TS_SYSCTRL_CLUSTERPWRSTAT_ACTIVE_PORTIONS_LEN       4
#define TS_SYSCTRL_CLUSTERPWRSTAT_ACTIVE_PORTIONS_OFFSET    20
#define TS_SYSCTRL_CLUSTER_OFF_FLUSH_CACHE_VALID_LEN        1
#define TS_SYSCTRL_CLUSTER_OFF_FLUSH_CACHE_VALID_OFFSET     19
#define TS_SYSCTRL_CLUSTER_CURRENT_STATE_FLUSH_CACHE_LEN    3
#define TS_SYSCTRL_CLUSTER_CURRENT_STATE_FLUSH_CACHE_OFFSET 16
#define TS_SYSCTRL_FSM_CLUSTER_PSTATE_LEN                   7
#define TS_SYSCTRL_FSM_CLUSTER_PSTATE_OFFSET                6
#define TS_SYSCTRL_CLUSTER_CURRENT_STATE_LEN                6
#define TS_SYSCTRL_CLUSTER_CURRENT_STATE_OFFSET             0

#define TS_SYSCTRL_CORE_PACTIVE_LEN    18
#define TS_SYSCTRL_CORE_PACTIVE_OFFSET 12
#define TS_SYSCTRL_CORE_PSTATE_LEN     7
#define TS_SYSCTRL_CORE_PSTATE_OFFSET  4
#define TS_SYSCTRL_CORE_PREQ_LEN       1
#define TS_SYSCTRL_CORE_PREQ_OFFSET    2
#define TS_SYSCTRL_CORE_PDENY_LEN      1
#define TS_SYSCTRL_CORE_PDENY_OFFSET   1
#define TS_SYSCTRL_CORE_PACCEPT_LEN    1
#define TS_SYSCTRL_CORE_PACCEPT_OFFSET 0

#define TS_SYSCTRL_CORE_PSTATE0_LEN      6
#define TS_SYSCTRL_CORE_PSTATE0_OFFSET   4
#define TS_SYSCTRL_CURRENT_STATE0_LEN    4
#define TS_SYSCTRL_CURRENT_STATE0_OFFSET 0

#define TS_SYSCTRL_FORCED_ON_SFONLY_COMPLETE_LEN    1
#define TS_SYSCTRL_FORCED_ON_SFONLY_COMPLETE_OFFSET 31
#define TS_SYSCTRL_CLUSTER_CAN_PD_LEN               1
#define TS_SYSCTRL_CLUSTER_CAN_PD_OFFSET            28
#define TS_SYSCTRL_CLUSTER_PDENY_TO_SYS_LEN         1
#define TS_SYSCTRL_CLUSTER_PDENY_TO_SYS_OFFSET      24
#define TS_SYSCTRL_CLUSTER_PACCEPT_TO_SYS_LEN       1
#define TS_SYSCTRL_CLUSTER_PACCEPT_TO_SYS_OFFSET    20
#define TS_SYSCTRL_CLUSTER_PACTIVE_TO_SYS_LEN       20
#define TS_SYSCTRL_CLUSTER_PACTIVE_TO_SYS_OFFSET    0

#define TS_SYSCTRL_CORE_CAN_PD_LEN       1
#define TS_SYSCTRL_CORE_CAN_PD_OFFSET    28
#define TS_SYSCTRL_PDENY_TO_SYS_LEN      1
#define TS_SYSCTRL_PDENY_TO_SYS_OFFSET   24
#define TS_SYSCTRL_PACCEPT_TO_SYS_LEN    1
#define TS_SYSCTRL_PACCEPT_TO_SYS_OFFSET 20
#define TS_SYSCTRL_PACTIVE_TO_SYS_LEN    18
#define TS_SYSCTRL_PACTIVE_TO_SYS_OFFSET 0

#define TS_SYSCTRL_TS_CPU_ID_VERSION_LEN    32
#define TS_SYSCTRL_TS_CPU_ID_VERSION_OFFSET 0

#define TS_SYSCTRL_SPNIDEN_FCM_LEN    1
#define TS_SYSCTRL_SPNIDEN_FCM_OFFSET 3
#define TS_SYSCTRL_SPIDEN_FCM_LEN     1
#define TS_SYSCTRL_SPIDEN_FCM_OFFSET  2
#define TS_SYSCTRL_NIDEN_FCM_LEN      1
#define TS_SYSCTRL_NIDEN_FCM_OFFSET   1
#define TS_SYSCTRL_DBGEN_FCM_LEN      1
#define TS_SYSCTRL_DBGEN_FCM_OFFSET   0

#define TS_SYSCTRL_CLUSTERIDAFF3_FCM_LEN    8
#define TS_SYSCTRL_CLUSTERIDAFF3_FCM_OFFSET 8
#define TS_SYSCTRL_CLUSTERIDAFF2_FCM_LEN    8
#define TS_SYSCTRL_CLUSTERIDAFF2_FCM_OFFSET 0

#define TS_SYSCTRL_PROTECTED_NSAID_EN_LEN       1
#define TS_SYSCTRL_PROTECTED_NSAID_EN_OFFSET    8
#define TS_SYSCTRL_PWAKEUP_BYPASS_LEN           1
#define TS_SYSCTRL_PWAKEUP_BYPASS_OFFSET        7
#define TS_SYSCTRL_SC_CORE_IDLE_SEL_LEN         1
#define TS_SYSCTRL_SC_CORE_IDLE_SEL_OFFSET      6
#define TS_SYSCTRL_SC_CORE_IDLE_LEN             1
#define TS_SYSCTRL_SC_CORE_IDLE_OFFSET          5
#define TS_SYSCTRL_AXIAW_NONCACHE_BYPASS_LEN    1
#define TS_SYSCTRL_AXIAW_NONCACHE_BYPASS_OFFSET 4
#define TS_SYSCTRL_AXIAR_NONCACHE_BYPASS_LEN    1
#define TS_SYSCTRL_AXIAR_NONCACHE_BYPASS_OFFSET 3
#define TS_SYSCTRL_SECURE_DEBUG_EN_LEN          1
#define TS_SYSCTRL_SECURE_DEBUG_EN_OFFSET       2
#define TS_SYSCTRL_AXI_AXPROT2_BYPASS_LEN       1
#define TS_SYSCTRL_AXI_AXPROT2_BYPASS_OFFSET    1
#define TS_SYSCTRL_AXI_ID_BYPASS_LEN            1
#define TS_SYSCTRL_AXI_ID_BYPASS_OFFSET         0

#define TS_SYSCTRL_TS_IDLE_DIV_BYPASS_LEN      1
#define TS_SYSCTRL_TS_IDLE_DIV_BYPASS_OFFSET   31
#define TS_SYSCTRL_TS_DIV_IDLE_CFG_LEN         6
#define TS_SYSCTRL_TS_DIV_IDLE_CFG_OFFSET      24
#define TS_SYSCTRL_TS_AUTO_WAIT_OUT_CFG_LEN    10
#define TS_SYSCTRL_TS_AUTO_WAIT_OUT_CFG_OFFSET 12
#define TS_SYSCTRL_TS_AUTO_WAIT_IN_CFG_LEN     10
#define TS_SYSCTRL_TS_AUTO_WAIT_IN_CFG_OFFSET  0

#define TS_SYSCTRL_DIV_WDOG_LEN                  2
#define TS_SYSCTRL_DIV_WDOG_OFFSET               6
#define TS_SYSCTRL_DIV_TIMER_LEN                 2
#define TS_SYSCTRL_DIV_TIMER_OFFSET              4
#define TS_SYSCTRL_SC_DW_AXI_AUTO_GATE_EN_LEN    1
#define TS_SYSCTRL_SC_DW_AXI_AUTO_GATE_EN_OFFSET 0

#define TS_SYSCTRL_SC_AXIECS0_DLOCK_CLEAR_LEN    1
#define TS_SYSCTRL_SC_AXIECS0_DLOCK_CLEAR_OFFSET 0

#define TS_SYSCTRL_RVBARADDR0_FCM_31_2__LEN    30
#define TS_SYSCTRL_RVBARADDR0_FCM_31_2__OFFSET 2

#define TS_SYSCTRL_VINITHI_FCM_LEN              1
#define TS_SYSCTRL_VINITHI_FCM_OFFSET           10
#define TS_SYSCTRL_AA64NAA32_FCM_LEN            1
#define TS_SYSCTRL_AA64NAA32_FCM_OFFSET         9
#define TS_SYSCTRL_GICCDISABLE_FCM_LEN          1
#define TS_SYSCTRL_GICCDISABLE_FCM_OFFSET       8
#define TS_SYSCTRL_RVBARADDR0_FCM_39_32__LEN    8
#define TS_SYSCTRL_RVBARADDR0_FCM_39_32__OFFSET 0

#define TS_SYSCTRL_ICG_EN_MBIST_CORE_LEN       1
#define TS_SYSCTRL_ICG_EN_MBIST_CORE_OFFSET    7
#define TS_SYSCTRL_ICG_EN_MBIST_FCM_PPU_LEN    1
#define TS_SYSCTRL_ICG_EN_MBIST_FCM_PPU_OFFSET 6
#define TS_SYSCTRL_ICG_EN_FCM_PERIPH_LEN       1
#define TS_SYSCTRL_ICG_EN_FCM_PERIPH_OFFSET    5
#define TS_SYSCTRL_ICG_EN_FCM_GIC_LEN          1
#define TS_SYSCTRL_ICG_EN_FCM_GIC_OFFSET       4
#define TS_SYSCTRL_ICG_EN_FCM_ATB_LEN          1
#define TS_SYSCTRL_ICG_EN_FCM_ATB_OFFSET       3
#define TS_SYSCTRL_ICG_EN_DBG_APB_LEN          1
#define TS_SYSCTRL_ICG_EN_DBG_APB_OFFSET       2
#define TS_SYSCTRL_ICG_EN_FCM_SCU_LEN          1
#define TS_SYSCTRL_ICG_EN_FCM_SCU_OFFSET       1
#define TS_SYSCTRL_ICG_EN_FCM_CORE_LEN         1
#define TS_SYSCTRL_ICG_EN_FCM_CORE_OFFSET      0

#define TS_SYSCTRL_ICG_DIS_MBIST_CORE_LEN       1
#define TS_SYSCTRL_ICG_DIS_MBIST_CORE_OFFSET    7
#define TS_SYSCTRL_ICG_DIS_MBIST_FCM_PPU_LEN    1
#define TS_SYSCTRL_ICG_DIS_MBIST_FCM_PPU_OFFSET 6
#define TS_SYSCTRL_ICG_DIS_FCM_PERIPH_LEN       1
#define TS_SYSCTRL_ICG_DIS_FCM_PERIPH_OFFSET    5
#define TS_SYSCTRL_ICG_DIS_FCM_GIC_LEN          1
#define TS_SYSCTRL_ICG_DIS_FCM_GIC_OFFSET       4
#define TS_SYSCTRL_ICG_DIS_FCM_ATB_LEN          1
#define TS_SYSCTRL_ICG_DIS_FCM_ATB_OFFSET       3
#define TS_SYSCTRL_ICG_DIS_DBG_APB_LEN          1
#define TS_SYSCTRL_ICG_DIS_DBG_APB_OFFSET       2
#define TS_SYSCTRL_ICG_DIS_FCM_SCU_LEN          1
#define TS_SYSCTRL_ICG_DIS_FCM_SCU_OFFSET       1
#define TS_SYSCTRL_ICG_DIS_FCM_CORE_LEN         1
#define TS_SYSCTRL_ICG_DIS_FCM_CORE_OFFSET      0

#define TS_SYSCTRL_ICG_ST_MBIST_CORE_LEN       1
#define TS_SYSCTRL_ICG_ST_MBIST_CORE_OFFSET    7
#define TS_SYSCTRL_ICG_ST_MBIST_FCM_PPU_LEN    1
#define TS_SYSCTRL_ICG_ST_MBIST_FCM_PPU_OFFSET 6
#define TS_SYSCTRL_ICG_ST_FCM_PERIPH_LEN       1
#define TS_SYSCTRL_ICG_ST_FCM_PERIPH_OFFSET    5
#define TS_SYSCTRL_ICG_ST_FCM_GIC_LEN          1
#define TS_SYSCTRL_ICG_ST_FCM_GIC_OFFSET       4
#define TS_SYSCTRL_ICG_ST_FCM_ATB_LEN          1
#define TS_SYSCTRL_ICG_ST_FCM_ATB_OFFSET       3
#define TS_SYSCTRL_ICG_ST_DBG_APB_LEN          1
#define TS_SYSCTRL_ICG_ST_DBG_APB_OFFSET       2
#define TS_SYSCTRL_ICG_ST_FCM_SCU_LEN          1
#define TS_SYSCTRL_ICG_ST_FCM_SCU_OFFSET       1
#define TS_SYSCTRL_ICG_ST_FCM_CORE_LEN         1
#define TS_SYSCTRL_ICG_ST_FCM_CORE_OFFSET      0

#define TS_SYSCTRL_RST_REQ_CORE_FSM_LEN        1
#define TS_SYSCTRL_RST_REQ_CORE_FSM_OFFSET     10
#define TS_SYSCTRL_RST_REQ_FCM_FSM_LEN         1
#define TS_SYSCTRL_RST_REQ_FCM_FSM_OFFSET      9
#define TS_SYSCTRL_RST_REQ_FCM_MBIST_LEN       1
#define TS_SYSCTRL_RST_REQ_FCM_MBIST_OFFSET    8
#define TS_SYSCTRL_RST_REQ_FCM_PERIPH_LEN      1
#define TS_SYSCTRL_RST_REQ_FCM_PERIPH_OFFSET   7
#define TS_SYSCTRL_RST_REQ_FCM_GIC_LEN         1
#define TS_SYSCTRL_RST_REQ_FCM_GIC_OFFSET      6
#define TS_SYSCTRL_RST_REQ_FCM_ATB_LEN         1
#define TS_SYSCTRL_RST_REQ_FCM_ATB_OFFSET      5
#define TS_SYSCTRL_RST_REQ_FCM_SCU_LEN         1
#define TS_SYSCTRL_RST_REQ_FCM_SCU_OFFSET      4
#define TS_SYSCTRL_RST_REQ_FCM_SCU_POR_LEN     1
#define TS_SYSCTRL_RST_REQ_FCM_SCU_POR_OFFSET  3
#define TS_SYSCTRL_RST_REQ_FCM_DBG_APB_LEN     1
#define TS_SYSCTRL_RST_REQ_FCM_DBG_APB_OFFSET  2
#define TS_SYSCTRL_RST_REQ_FCM_CORE_LEN        1
#define TS_SYSCTRL_RST_REQ_FCM_CORE_OFFSET     1
#define TS_SYSCTRL_RST_REQ_FCM_CORE_POR_LEN    1
#define TS_SYSCTRL_RST_REQ_FCM_CORE_POR_OFFSET 0

#define TS_SYSCTRL_RST_DIS_CORE_FSM_LEN        1
#define TS_SYSCTRL_RST_DIS_CORE_FSM_OFFSET     10
#define TS_SYSCTRL_RST_DIS_FCM_FSM_LEN         1
#define TS_SYSCTRL_RST_DIS_FCM_FSM_OFFSET      9
#define TS_SYSCTRL_RST_DIS_FCM_MBIST_LEN       1
#define TS_SYSCTRL_RST_DIS_FCM_MBIST_OFFSET    8
#define TS_SYSCTRL_RST_DIS_FCM_PERIPH_LEN      1
#define TS_SYSCTRL_RST_DIS_FCM_PERIPH_OFFSET   7
#define TS_SYSCTRL_RST_DIS_FCM_GIC_LEN         1
#define TS_SYSCTRL_RST_DIS_FCM_GIC_OFFSET      6
#define TS_SYSCTRL_RST_DIS_FCM_ATB_LEN         1
#define TS_SYSCTRL_RST_DIS_FCM_ATB_OFFSET      5
#define TS_SYSCTRL_RST_DIS_FCM_SCU_LEN         1
#define TS_SYSCTRL_RST_DIS_FCM_SCU_OFFSET      4
#define TS_SYSCTRL_RST_DIS_FCM_SCU_POR_LEN     1
#define TS_SYSCTRL_RST_DIS_FCM_SCU_POR_OFFSET  3
#define TS_SYSCTRL_RST_DIS_FCM_DBG_APB_LEN     1
#define TS_SYSCTRL_RST_DIS_FCM_DBG_APB_OFFSET  2
#define TS_SYSCTRL_RST_DIS_FCM_CORE_LEN        1
#define TS_SYSCTRL_RST_DIS_FCM_CORE_OFFSET     1
#define TS_SYSCTRL_RST_DIS_FCM_CORE_POR_LEN    1
#define TS_SYSCTRL_RST_DIS_FCM_CORE_POR_OFFSET 0

#define TS_SYSCTRL_SRST_REQ_CORE_FSM_LEN        1
#define TS_SYSCTRL_SRST_REQ_CORE_FSM_OFFSET     10
#define TS_SYSCTRL_SRST_REQ_FCM_FSM_LEN         1
#define TS_SYSCTRL_SRST_REQ_FCM_FSM_OFFSET      9
#define TS_SYSCTRL_SRST_REQ_FCM_MBIST_LEN       1
#define TS_SYSCTRL_SRST_REQ_FCM_MBIST_OFFSET    8
#define TS_SYSCTRL_SRST_REQ_FCM_PERIPH_LEN      1
#define TS_SYSCTRL_SRST_REQ_FCM_PERIPH_OFFSET   7
#define TS_SYSCTRL_SRST_REQ_FCM_GIC_LEN         1
#define TS_SYSCTRL_SRST_REQ_FCM_GIC_OFFSET      6
#define TS_SYSCTRL_SRST_REQ_FCM_ATB_LEN         1
#define TS_SYSCTRL_SRST_REQ_FCM_ATB_OFFSET      5
#define TS_SYSCTRL_SRST_REQ_FCM_SCU_LEN         1
#define TS_SYSCTRL_SRST_REQ_FCM_SCU_OFFSET      4
#define TS_SYSCTRL_SRST_REQ_FCM_SCU_POR_LEN     1
#define TS_SYSCTRL_SRST_REQ_FCM_SCU_POR_OFFSET  3
#define TS_SYSCTRL_SRST_REQ_FCM_DBG_APB_LEN     1
#define TS_SYSCTRL_SRST_REQ_FCM_DBG_APB_OFFSET  2
#define TS_SYSCTRL_SRST_REQ_FCM_CORE_LEN        1
#define TS_SYSCTRL_SRST_REQ_FCM_CORE_OFFSET     1
#define TS_SYSCTRL_SRST_REQ_FCM_CORE_POR_LEN    1
#define TS_SYSCTRL_SRST_REQ_FCM_CORE_POR_OFFSET 0

#define TS_SYSCTRL_TS_CPU_ARQOS_LEN    4
#define TS_SYSCTRL_TS_CPU_ARQOS_OFFSET 12
#define TS_SYSCTRL_TS_CPU_AWQOS_LEN    4
#define TS_SYSCTRL_TS_CPU_AWQOS_OFFSET 8
#define TS_SYSCTRL_TS_BS_ARQOS_LEN     4
#define TS_SYSCTRL_TS_BS_ARQOS_OFFSET  4
#define TS_SYSCTRL_TS_BS_AWQOS_LEN     4
#define TS_SYSCTRL_TS_BS_AWQOS_OFFSET  0

#define TS_SYSCTRL_SC_TIMER_EN_LEN    1
#define TS_SYSCTRL_SC_TIMER_EN_OFFSET 0



#define TS_SYSCTRL_TS_DB_MEM_CTRL_SP_LEN    7
#define TS_SYSCTRL_TS_DB_MEM_CTRL_SP_OFFSET 0

#define TS_SYSCTRL_TS_SRAM_MEM_CTRL_SP_LEN    7
#define TS_SYSCTRL_TS_SRAM_MEM_CTRL_SP_OFFSET 0

#define TS_SYSCTRL_MST_PRIORITY_S5_LEN    3
#define TS_SYSCTRL_MST_PRIORITY_S5_OFFSET 20
#define TS_SYSCTRL_MST_PRIORITY_S4_LEN    3
#define TS_SYSCTRL_MST_PRIORITY_S4_OFFSET 17
#define TS_SYSCTRL_MST_PRIORITY_S3_LEN    3
#define TS_SYSCTRL_MST_PRIORITY_S3_OFFSET 14
#define TS_SYSCTRL_MST_PRIORITY_S2_LEN    3
#define TS_SYSCTRL_MST_PRIORITY_S2_OFFSET 11
#define TS_SYSCTRL_MST_PRIORITY_S1_LEN    3
#define TS_SYSCTRL_MST_PRIORITY_S1_OFFSET 8
#define TS_SYSCTRL_MST_PRIORITY_M3_LEN    2
#define TS_SYSCTRL_MST_PRIORITY_M3_OFFSET 4
#define TS_SYSCTRL_MST_PRIORITY_M2_LEN    2
#define TS_SYSCTRL_MST_PRIORITY_M2_OFFSET 2
#define TS_SYSCTRL_MST_PRIORITY_M1_LEN    2
#define TS_SYSCTRL_MST_PRIORITY_M1_OFFSET 0

#define TS_SYSCTRL_ANANKE_BTAC0_CORE0_LEN    32
#define TS_SYSCTRL_ANANKE_BTAC0_CORE0_OFFSET 0

#define TS_SYSCTRL_ANANKE_BTAC1_CORE0_LEN    32
#define TS_SYSCTRL_ANANKE_BTAC1_CORE0_OFFSET 0

#define TS_SYSCTRL_ANANKE_L1D_DATA_CORE0_LEN    32
#define TS_SYSCTRL_ANANKE_L1D_DATA_CORE0_OFFSET 0

#define TS_SYSCTRL_ANANKE_L1D_TAG_CORE0_LEN    32
#define TS_SYSCTRL_ANANKE_L1D_TAG_CORE0_OFFSET 0

#define TS_SYSCTRL_ANANKE_L1D_DIRTY_CORE0_LEN    32
#define TS_SYSCTRL_ANANKE_L1D_DIRTY_CORE0_OFFSET 0

#define TS_SYSCTRL_ANANKE_L1I_DATA_CORE0_LEN    32
#define TS_SYSCTRL_ANANKE_L1I_DATA_CORE0_OFFSET 0

#define TS_SYSCTRL_ANANKE_L1I_TAG_CORE0_LEN    32
#define TS_SYSCTRL_ANANKE_L1I_TAG_CORE0_OFFSET 0

#define TS_SYSCTRL_ANANKE_L2_L2DB_CORE0_LEN    32
#define TS_SYSCTRL_ANANKE_L2_L2DB_CORE0_OFFSET 0

#define TS_SYSCTRL_ANANKE_TLB_TAG_CORE0_LEN    32
#define TS_SYSCTRL_ANANKE_TLB_TAG_CORE0_OFFSET 0

#define TS_SYSCTRL_ANANKE_TLB_DATA_CORE0_LEN    32
#define TS_SYSCTRL_ANANKE_TLB_DATA_CORE0_OFFSET 0

#define TS_SYSCTRL_SCU_SF_LEN    32
#define TS_SYSCTRL_SCU_SF_OFFSET 0

#define TS_SYSCTRL_SCU_LTDB_LEN    32
#define TS_SYSCTRL_SCU_LTDB_OFFSET 0

#define TS_SYSCTRL_SC_RESET_PROT_DISABLE_LEN    1
#define TS_SYSCTRL_SC_RESET_PROT_DISABLE_OFFSET 0





#define TS_SYSCTRL_ICG_EN_DPM_LEN      1
#define TS_SYSCTRL_ICG_EN_DPM_OFFSET   5
#define TS_SYSCTRL_ICG_EN_DB_LEN       1
#define TS_SYSCTRL_ICG_EN_DB_OFFSET    4
#define TS_SYSCTRL_ICG_EN_SRAM_LEN     1
#define TS_SYSCTRL_ICG_EN_SRAM_OFFSET  3
#define TS_SYSCTRL_ICG_EN_BS_LEN       1
#define TS_SYSCTRL_ICG_EN_BS_OFFSET    2
#define TS_SYSCTRL_ICG_EN_TIMER_LEN    1
#define TS_SYSCTRL_ICG_EN_TIMER_OFFSET 1
#define TS_SYSCTRL_ICG_EN_WDOG_LEN     1
#define TS_SYSCTRL_ICG_EN_WDOG_OFFSET  0

#define TS_SYSCTRL_ICG_DIS_DPM_LEN      1
#define TS_SYSCTRL_ICG_DIS_DPM_OFFSET   5
#define TS_SYSCTRL_ICG_DIS_DB_LEN       1
#define TS_SYSCTRL_ICG_DIS_DB_OFFSET    4
#define TS_SYSCTRL_ICG_DIS_SRAM_LEN     1
#define TS_SYSCTRL_ICG_DIS_SRAM_OFFSET  3
#define TS_SYSCTRL_ICG_DIS_BS_LEN       1
#define TS_SYSCTRL_ICG_DIS_BS_OFFSET    2
#define TS_SYSCTRL_ICG_DIS_TIMER_LEN    1
#define TS_SYSCTRL_ICG_DIS_TIMER_OFFSET 1
#define TS_SYSCTRL_ICG_DIS_WDOG_LEN     1
#define TS_SYSCTRL_ICG_DIS_WDOG_OFFSET  0

#define TS_SYSCTRL_ICG_ST_DPM_LEN      1
#define TS_SYSCTRL_ICG_ST_DPM_OFFSET   5
#define TS_SYSCTRL_ICG_ST_DB_LEN       1
#define TS_SYSCTRL_ICG_ST_DB_OFFSET    4
#define TS_SYSCTRL_ICG_ST_SRAM_LEN     1
#define TS_SYSCTRL_ICG_ST_SRAM_OFFSET  3
#define TS_SYSCTRL_ICG_ST_BS_LEN       1
#define TS_SYSCTRL_ICG_ST_BS_OFFSET    2
#define TS_SYSCTRL_ICG_ST_TIMER_LEN    1
#define TS_SYSCTRL_ICG_ST_TIMER_OFFSET 1
#define TS_SYSCTRL_ICG_ST_WDOG_LEN     1
#define TS_SYSCTRL_ICG_ST_WDOG_OFFSET  0

#define TS_SYSCTRL_RST_REQ_DPM_LEN      1
#define TS_SYSCTRL_RST_REQ_DPM_OFFSET   5
#define TS_SYSCTRL_RST_REQ_DB_LEN       1
#define TS_SYSCTRL_RST_REQ_DB_OFFSET    4
#define TS_SYSCTRL_RST_REQ_SRAM_LEN     1
#define TS_SYSCTRL_RST_REQ_SRAM_OFFSET  3
#define TS_SYSCTRL_RST_REQ_BS_LEN       1
#define TS_SYSCTRL_RST_REQ_BS_OFFSET    2
#define TS_SYSCTRL_RST_REQ_TIMER_LEN    1
#define TS_SYSCTRL_RST_REQ_TIMER_OFFSET 1
#define TS_SYSCTRL_RST_REQ_WDOG_LEN     1
#define TS_SYSCTRL_RST_REQ_WDOG_OFFSET  0

#define TS_SYSCTRL_RST_DIS_DPM_LEN      1
#define TS_SYSCTRL_RST_DIS_DPM_OFFSET   5
#define TS_SYSCTRL_RST_DIS_DB_LEN       1
#define TS_SYSCTRL_RST_DIS_DB_OFFSET    4
#define TS_SYSCTRL_RST_DIS_SRAM_LEN     1
#define TS_SYSCTRL_RST_DIS_SRAM_OFFSET  3
#define TS_SYSCTRL_RST_DIS_BS_LEN       1
#define TS_SYSCTRL_RST_DIS_BS_OFFSET    2
#define TS_SYSCTRL_RST_DIS_TIMER_LEN    1
#define TS_SYSCTRL_RST_DIS_TIMER_OFFSET 1
#define TS_SYSCTRL_RST_DIS_WDOG_LEN     1
#define TS_SYSCTRL_RST_DIS_WDOG_OFFSET  0

#define TS_SYSCTRL_SRST_REQ_DPM_LEN      1
#define TS_SYSCTRL_SRST_REQ_DPM_OFFSET   5
#define TS_SYSCTRL_SRST_REQ_DB_LEN       1
#define TS_SYSCTRL_SRST_REQ_DB_OFFSET    4
#define TS_SYSCTRL_SRST_REQ_SRAM_LEN     1
#define TS_SYSCTRL_SRST_REQ_SRAM_OFFSET  3
#define TS_SYSCTRL_SRST_REQ_BS_LEN       1
#define TS_SYSCTRL_SRST_REQ_BS_OFFSET    2
#define TS_SYSCTRL_SRST_REQ_TIMER_LEN    1
#define TS_SYSCTRL_SRST_REQ_TIMER_OFFSET 1
#define TS_SYSCTRL_SRST_REQ_WDOG_LEN     1
#define TS_SYSCTRL_SRST_REQ_WDOG_OFFSET  0

#define TS_SYSCTRL_AW_STRMID_LEN    32
#define TS_SYSCTRL_AW_STRMID_OFFSET 0

#define TS_SYSCTRL_AW_TLB_LOCK_LEN        1
#define TS_SYSCTRL_AW_TLB_LOCK_OFFSET     31
#define TS_SYSCTRL_AW_SNPATTR_LEN         1
#define TS_SYSCTRL_AW_SNPATTR_OFFSET      30
#define TS_SYSCTRL_AW_SO_ID_LEN           3
#define TS_SYSCTRL_AW_SO_ID_OFFSET        27
#define TS_SYSCTRL_AW_SO_LEN              1
#define TS_SYSCTRL_AW_SO_OFFSET           26
#define TS_SYSCTRL_AW_STASH_LPID_LEN      8
#define TS_SYSCTRL_AW_STASH_LPID_OFFSET   18
#define TS_SYSCTRL_AW_STASH_LEN           1
#define TS_SYSCTRL_AW_STASH_OFFSET        17
#define TS_SYSCTRL_AW_ATOMIC_TYPE_LEN     2
#define TS_SYSCTRL_AW_ATOMIC_TYPE_OFFSET  15
#define TS_SYSCTRL_AW_CMD_TYPE_LEN        3
#define TS_SYSCTRL_AW_CMD_TYPE_OFFSET     12
#define TS_SYSCTRL_AW_TYPE_LEN            2
#define TS_SYSCTRL_AW_TYPE_OFFSET         10
#define TS_SYSCTRL_AW_TH_DIRECT_LEN       2
#define TS_SYSCTRL_AW_TH_DIRECT_OFFSET    8
#define TS_SYSCTRL_AW_TH_LEN              1
#define TS_SYSCTRL_AW_TH_OFFSET           7
#define TS_SYSCTRL_AW_NO_LEN              1
#define TS_SYSCTRL_AW_NO_OFFSET           5
#define TS_SYSCTRL_AW_FP_LEN              1
#define TS_SYSCTRL_AW_FP_OFFSET           4
#define TS_SYSCTRL_AW_CLEANINVALID_LEN    1
#define TS_SYSCTRL_AW_CLEANINVALID_OFFSET 3
#define TS_SYSCTRL_AW_FNA_LEN             1
#define TS_SYSCTRL_AW_FNA_OFFSET          2
#define TS_SYSCTRL_AW_FA_LEN              1
#define TS_SYSCTRL_AW_FA_OFFSET           1
#define TS_SYSCTRL_AW_SSV_LEN             1
#define TS_SYSCTRL_AW_SSV_OFFSET          0

#define TS_SYSCTRL_AW_STASH_NID_VALID_LEN     1
#define TS_SYSCTRL_AW_STASH_NID_VALID_OFFSET  3
#define TS_SYSCTRL_AW_STASH_LPID_VALID_LEN    1
#define TS_SYSCTRL_AW_STASH_LPID_VALID_OFFSET 2
#define TS_SYSCTRL_AW_TLB_UNLOCK_LEN          1
#define TS_SYSCTRL_AW_TLB_UNLOCK_OFFSET       0

#define TS_SYSCTRL_AR_STRMID_LEN    32
#define TS_SYSCTRL_AR_STRMID_OFFSET 0

#define TS_SYSCTRL_AR_TLB_LOCK_LEN        1
#define TS_SYSCTRL_AR_TLB_LOCK_OFFSET     31
#define TS_SYSCTRL_AR_SNPATTR_LEN         1
#define TS_SYSCTRL_AR_SNPATTR_OFFSET      30
#define TS_SYSCTRL_AR_SO_ID_LEN           3
#define TS_SYSCTRL_AR_SO_ID_OFFSET        27
#define TS_SYSCTRL_AR_SO_LEN              1
#define TS_SYSCTRL_AR_SO_OFFSET           26
#define TS_SYSCTRL_AR_STASH_LPID_LEN      8
#define TS_SYSCTRL_AR_STASH_LPID_OFFSET   18
#define TS_SYSCTRL_AR_STASH_LEN           1
#define TS_SYSCTRL_AR_STASH_OFFSET        17
#define TS_SYSCTRL_AR_ATOMIC_TYPE_LEN     2
#define TS_SYSCTRL_AR_ATOMIC_TYPE_OFFSET  15
#define TS_SYSCTRL_AR_CMD_TYPE_LEN        3
#define TS_SYSCTRL_AR_CMD_TYPE_OFFSET     12
#define TS_SYSCTRL_AR_TYPE_LEN            2
#define TS_SYSCTRL_AR_TYPE_OFFSET         10
#define TS_SYSCTRL_AR_TH_DIRECT_LEN       2
#define TS_SYSCTRL_AR_TH_DIRECT_OFFSET    8
#define TS_SYSCTRL_AR_TH_LEN              1
#define TS_SYSCTRL_AR_TH_OFFSET           7
#define TS_SYSCTRL_AR_NO_LEN              1
#define TS_SYSCTRL_AR_NO_OFFSET           5
#define TS_SYSCTRL_AR_FP_LEN              1
#define TS_SYSCTRL_AR_FP_OFFSET           4
#define TS_SYSCTRL_AR_CLEANINVALID_LEN    1
#define TS_SYSCTRL_AR_CLEANINVALID_OFFSET 3
#define TS_SYSCTRL_AR_FNA_LEN             1
#define TS_SYSCTRL_AR_FNA_OFFSET          2
#define TS_SYSCTRL_AR_FA_LEN              1
#define TS_SYSCTRL_AR_FA_OFFSET           1
#define TS_SYSCTRL_AR_SSV_LEN             1
#define TS_SYSCTRL_AR_SSV_OFFSET          0

#define TS_SYSCTRL_AR_STASH_NID_VALID_LEN     1
#define TS_SYSCTRL_AR_STASH_NID_VALID_OFFSET  3
#define TS_SYSCTRL_AR_STASH_LPID_VALID_LEN    1
#define TS_SYSCTRL_AR_STASH_LPID_VALID_OFFSET 2
#define TS_SYSCTRL_AR_TLB_UNLOCK_LEN          1
#define TS_SYSCTRL_AR_TLB_UNLOCK_OFFSET       0





#define TS_SYSCTRL_TS_SIGNAL_MONITOR_LEN    16
#define TS_SYSCTRL_TS_SIGNAL_MONITOR_OFFSET 0

#define TS_SYSCTRL_NFIQ_TEST_LEN            1
#define TS_SYSCTRL_NFIQ_TEST_OFFSET         16
#define TS_SYSCTRL_NIRQ_TEST_LEN            1
#define TS_SYSCTRL_NIRQ_TEST_OFFSET         15
#define TS_SYSCTRL_DBGNOPWRDWN_PATCH_LEN    1
#define TS_SYSCTRL_DBGNOPWRDWN_PATCH_OFFSET 14
#define TS_SYSCTRL_PMUSNAPSHOTREQ_LEN       1
#define TS_SYSCTRL_PMUSNAPSHOTREQ_OFFSET    13
#define TS_SYSCTRL_TIMER_HALT_EN_LEN        1
#define TS_SYSCTRL_TIMER_HALT_EN_OFFSET     11
#define TS_SYSCTRL_WDOG_HALT_EN_LEN         1
#define TS_SYSCTRL_WDOG_HALT_EN_OFFSET      10

#define TS_SYSCTRL_PCLK_DBG_Q_CHANNEL_CFGCNT_LEN    7
#define TS_SYSCTRL_PCLK_DBG_Q_CHANNEL_CFGCNT_OFFSET 24
#define TS_SYSCTRL_DEBUG_PWR_Q_CHANNEL_QREQN_LEN    1
#define TS_SYSCTRL_DEBUG_PWR_Q_CHANNEL_QREQN_OFFSET 5
#define TS_SYSCTRL_PCLK_DBG_Q_CHANNEL_EN_LEN        1
#define TS_SYSCTRL_PCLK_DBG_Q_CHANNEL_EN_OFFSET     4
#define TS_SYSCTRL_GICCLK_Q_CHANNEL_EN_LEN          1
#define TS_SYSCTRL_GICCLK_Q_CHANNEL_EN_OFFSET       3
#define TS_SYSCTRL_PCLK_Q_CHANNEL_EN_LEN            1
#define TS_SYSCTRL_PCLK_Q_CHANNEL_EN_OFFSET         2
#define TS_SYSCTRL_ATCLK_Q_CHANNEL_EN_LEN           1
#define TS_SYSCTRL_ATCLK_Q_CHANNEL_EN_OFFSET        1
#define TS_SYSCTRL_SCLK_Q_CHANNEL_EN_LEN            1
#define TS_SYSCTRL_SCLK_Q_CHANNEL_EN_OFFSET         0

#define TS_SYSCTRL_GICCLK_Q_CHANNEL_CFGCNT_LEN    7
#define TS_SYSCTRL_GICCLK_Q_CHANNEL_CFGCNT_OFFSET 24
#define TS_SYSCTRL_PCLK_Q_CHANNEL_CFGCNT_LEN      7
#define TS_SYSCTRL_PCLK_Q_CHANNEL_CFGCNT_OFFSET   16
#define TS_SYSCTRL_ATCLK_Q_CHANNEL_CFGCNT_LEN     7
#define TS_SYSCTRL_ATCLK_Q_CHANNEL_CFGCNT_OFFSET  8
#define TS_SYSCTRL_SCLK_Q_CHANNEL_CFGCNT_LEN      7
#define TS_SYSCTRL_SCLK_Q_CHANNEL_CFGCNT_OFFSET   0

#define TS_SYSCTRL_FCM_P_CHANNEL_ENABLE_LEN            1
#define TS_SYSCTRL_FCM_P_CHANNEL_ENABLE_OFFSET         31
#define TS_SYSCTRL_CLUSTER_PACTIVE_SEL_LEN             2
#define TS_SYSCTRL_CLUSTER_PACTIVE_SEL_OFFSET          24
#define TS_SYSCTRL_CLUSTER_PSTATE_FROM_SYS_LEN         7
#define TS_SYSCTRL_CLUSTER_PSTATE_FROM_SYS_OFFSET      16
#define TS_SYSCTRL_CLUSTER_PREQ_FROM_SYS_LEN           1
#define TS_SYSCTRL_CLUSTER_PREQ_FROM_SYS_OFFSET        15
#define TS_SYSCTRL_FORCE_ON_TO_SFONLY_ON_LEN           1
#define TS_SYSCTRL_FORCE_ON_TO_SFONLY_ON_OFFSET        12
#define TS_SYSCTRL_FORCE_OFF_TO_ON_LEN                 1
#define TS_SYSCTRL_FORCE_OFF_TO_ON_OFFSET              11
#define TS_SYSCTRL_FORCE_FLUSH_CACHE_LEN               1
#define TS_SYSCTRL_FORCE_FLUSH_CACHE_OFFSET            10
#define TS_SYSCTRL_FORCE_DISABLE_OFF_LEN               1
#define TS_SYSCTRL_FORCE_DISABLE_OFF_OFFSET            9
#define TS_SYSCTRL_FORCE_ON_TO_SFONLY_ON_ENABLE_LEN    1
#define TS_SYSCTRL_FORCE_ON_TO_SFONLY_ON_ENABLE_OFFSET 8
#define TS_SYSCTRL_FCM_P_CHANNEL_INIT_PSTATE_LEN       7
#define TS_SYSCTRL_FCM_P_CHANNEL_INIT_PSTATE_OFFSET    0

#define TS_SYSCTRL_FCM_PCHANNEL_WAIT_CYCLE_DSLP_LEN    16
#define TS_SYSCTRL_FCM_PCHANNEL_WAIT_CYCLE_DSLP_OFFSET 16
#define TS_SYSCTRL_FCM_PCHANNEL_WAIT_CYCLE_SD_LEN      16
#define TS_SYSCTRL_FCM_PCHANNEL_WAIT_CYCLE_SD_OFFSET   0

#define TS_SYSCTRL_CORE0_P_CHANNEL_ENABLE_LEN         1
#define TS_SYSCTRL_CORE0_P_CHANNEL_ENABLE_OFFSET      31
#define TS_SYSCTRL_CORE0_MEM_CTRL_FROM_SYS_LEN        3
#define TS_SYSCTRL_CORE0_MEM_CTRL_FROM_SYS_OFFSET     28
#define TS_SYSCTRL_CORE0_PREQ_FROM_SYS_LEN            1
#define TS_SYSCTRL_CORE0_PREQ_FROM_SYS_OFFSET         24
#define TS_SYSCTRL_CORE0_PSTATE_FROM_SYS_LEN          6
#define TS_SYSCTRL_CORE0_PSTATE_FROM_SYS_OFFSET       16
#define TS_SYSCTRL_CORE0_P_CHANNEL_INIT_PSTATE_LEN    6
#define TS_SYSCTRL_CORE0_P_CHANNEL_INIT_PSTATE_OFFSET 0

#define TS_SYSCTRL_CORE0_PCHANNEL_WAIT_CYCLE_DSLP_LEN    16
#define TS_SYSCTRL_CORE0_PCHANNEL_WAIT_CYCLE_DSLP_OFFSET 0

#define TS_SYSCTRL_TEST_REG0_LEN    32
#define TS_SYSCTRL_TEST_REG0_OFFSET 0

#define TS_SYSCTRL_TEST_REG1_LEN    32
#define TS_SYSCTRL_TEST_REG1_OFFSET 0

#define TS_SYSCTRL_TEST_REG2_LEN    32
#define TS_SYSCTRL_TEST_REG2_OFFSET 0

#define TS_SYSCTRL_TEST_REG3_LEN    32
#define TS_SYSCTRL_TEST_REG3_OFFSET 0

#define TS_SYSCTRL_TEST_REG4_LEN    32
#define TS_SYSCTRL_TEST_REG4_OFFSET 0

#define TS_SYSCTRL_TEST_REG5_LEN    32
#define TS_SYSCTRL_TEST_REG5_OFFSET 0

#define TS_SYSCTRL_TEST_REG6_LEN    32
#define TS_SYSCTRL_TEST_REG6_OFFSET 0

#define TS_SYSCTRL_TEST_REG7_LEN    32
#define TS_SYSCTRL_TEST_REG7_OFFSET 0

#define TS_SYSCTRL_TEST_REG8_LEN    32
#define TS_SYSCTRL_TEST_REG8_OFFSET 0

#define TS_SYSCTRL_TEST_REG9_LEN    32
#define TS_SYSCTRL_TEST_REG9_OFFSET 0

#define TS_SYSCTRL_TEST_REG10_LEN    32
#define TS_SYSCTRL_TEST_REG10_OFFSET 0

#define TS_SYSCTRL_TEST_REG11_LEN    32
#define TS_SYSCTRL_TEST_REG11_OFFSET 0

#define TS_SYSCTRL_TEST_REG12_LEN    32
#define TS_SYSCTRL_TEST_REG12_OFFSET 0

#define TS_SYSCTRL_TEST_REG13_LEN    32
#define TS_SYSCTRL_TEST_REG13_OFFSET 0

#define TS_SYSCTRL_TEST_REG14_LEN    32
#define TS_SYSCTRL_TEST_REG14_OFFSET 0

#define TS_SYSCTRL_TEST_REG15_LEN    32
#define TS_SYSCTRL_TEST_REG15_OFFSET 0

#define TS_SYSCTRL_SEMA_REG0_LEN    32
#define TS_SYSCTRL_SEMA_REG0_OFFSET 0

#define TS_SYSCTRL_SEMA_REG1_LEN    32
#define TS_SYSCTRL_SEMA_REG1_OFFSET 0

#define TS_SYSCTRL_SEMA_REG2_LEN    32
#define TS_SYSCTRL_SEMA_REG2_OFFSET 0

#define TS_SYSCTRL_SEMA_REG3_LEN    32
#define TS_SYSCTRL_SEMA_REG3_OFFSET 0

#define TS_SYSCTRL_SEMA_REG4_LEN    32
#define TS_SYSCTRL_SEMA_REG4_OFFSET 0

#define TS_SYSCTRL_SEMA_REG5_LEN    32
#define TS_SYSCTRL_SEMA_REG5_OFFSET 0

#define TS_SYSCTRL_SEMA_REG6_LEN    32
#define TS_SYSCTRL_SEMA_REG6_OFFSET 0

#define TS_SYSCTRL_SEMA_REG7_LEN    32
#define TS_SYSCTRL_SEMA_REG7_OFFSET 0

#define TS_SYSCTRL_SEMA_REG8_LEN    32
#define TS_SYSCTRL_SEMA_REG8_OFFSET 0

#define TS_SYSCTRL_SEMA_REG9_LEN    32
#define TS_SYSCTRL_SEMA_REG9_OFFSET 0

#define TS_SYSCTRL_SEMA_REG10_LEN    32
#define TS_SYSCTRL_SEMA_REG10_OFFSET 0

#define TS_SYSCTRL_SEMA_REG11_LEN    32
#define TS_SYSCTRL_SEMA_REG11_OFFSET 0

#define TS_SYSCTRL_SEMA_REG12_LEN    32
#define TS_SYSCTRL_SEMA_REG12_OFFSET 0

#define TS_SYSCTRL_SEMA_REG13_LEN    32
#define TS_SYSCTRL_SEMA_REG13_OFFSET 0

#define TS_SYSCTRL_SEMA_REG14_LEN    32
#define TS_SYSCTRL_SEMA_REG14_OFFSET 0

#define TS_SYSCTRL_SEMA_REG15_LEN    32
#define TS_SYSCTRL_SEMA_REG15_OFFSET 0

#define TS_SYSCTRL_TEST_REG16_LEN    32
#define TS_SYSCTRL_TEST_REG16_OFFSET 0

#define TS_SYSCTRL_TEST_REG17_LEN    32
#define TS_SYSCTRL_TEST_REG17_OFFSET 0

#define TS_SYSCTRL_SCPROTREG_LEN    32
#define TS_SYSCTRL_SCPROTREG_OFFSET 0

#endif // __TS_SYSCTRL_REG_OFFSET_FIELD_H__
